The present invention relates to a multiport semiconductor memory device.
FIG. 22 shows a conventional dual-port RAM, in which one cycle is time-divided into two to provide access time periods dedicated to A port 12 and B port 13. Specifically, in the former half of the cycle, a chip enable signal /CEA for the A port 12 is put in a low level (selected) to allow access with an address ADRA, while in the latter half of the cycle, a chip enable signal /CEB for the B port 13 is put in a low level (selected) to allow access with an address ADRB. Therefore, even if both ports 12 and 13 happen to access the same address for write in the same cycle, such access attempts will not conflict with each other ideally due to the time-division processing. Japanese Laid-Open Patent Publication No. 7-175713 describes a method for controlling such access of different ports.
Although not shown in FIG. 22, a dual-port memory cell array 11 has a plurality of memory cells, each of which is connected with bit lines each for read and write via drain-source connection of relevant access transistors. A word line for sending an activation signal is connected to the gate of each access transistor. The activation signal is sent from each port to a word line corresponding to an address to which access is intended, to thereby turn ON the relevant access transistors. This brings relevant bit lines for write or read into conduction with the memory cell via the access transistors, enabling read or write of data.
However, even if the time-division processing is performed ideally, the conventional dual-port semiconductor memory device has the following problem. While processing for one port has not yet been finished, the other port may start access due to an error in the delay time in the ports or any other reason, and this may cause accessing to the same row address in the same cycle. Moreover, if one port is to perform read, the relevant word line of this read port will be activated. Since the relevant word line of the other port is also activated, the access transistors for the two ports will be turned ON simultaneously. This will result in the two ports being electrically connected to the same node of the memory cell via the access transistors, and thus the relevant bit line of the other port, which is unnecessary for the read operation of the one port, will become connected with the memory cell. That is, the bit lines of the two ports will be brought into conduction to each other, and as a result, the load of the bit line coupled to the other port will be added to the bit line of the one port that is to perform read.
As described above, the end part of processing of the previously accessing port may overlap the beginning part of processing of the subsequently accessing port in the same cycle, and as a result, the read bit line may be burdened with an unnecessary load of the bit line of the other port. This will cause a delay of a signal for read. To ensure the read data processing, therefore, the read time must be made long.
If the above event is not considered, and the time-division processing is uniformly applied to the case of occurrence of access to the same address from two ports in the same cycle as is applied to the other normal cases requiring no longer read time, the following problem will occur. That is, if the previously accessing port is a read port, the port will fail to secure a sufficient read time due to access from the subsequently accessing port of which processing overlaps the processing of the previously accessing port. If the subsequently accessing port is a read port, the read time will become long due to the previously accessing port and thus fail to secure a sufficient read time within the set cycle. In both cases, data processing will become uncertain.
The above problem will also arise in other multiport semiconductor memory devices having a plurality of ports other than two.